The present disclosure relates to electrical device manufacturing, and more particularly to semiconductor devices having strain based performance enhancements.
In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs). Scaling in intended to achieve compactness and to improve the operating performance by shrinking the overall dimensions and operating voltages of the device. With scaling increasingly reaching its physical limits, other methods of increasing performance of semiconductor devices have been contemplated, such as strain based performance enhancements.